On the Analog CMOS Peak Detect and Hold Circuit Part 2. Offset-Free Rail-to-Rail and Derandomizing Configuration1

An analog CMOS peak detect and hold (PDH) circuit which combines high speed and accuracy, rail-to-rail sensing and driving, low power, and buffering is presented. It is based on a configuration that cancels the major error sources of the classical CMOS PDH, including offset and common mode gain, by re-using the same amplifier for tracking, peak sensing, and output buffering. By virtue of its high absolute accuracy, two or more PDHs can be used in parallel to serve as a data-driven analog memory for derandomization. First experimental results on the new peak detector and derandomizer (PDD) circuit, fabricated in 0.35 μm CMOS technology, include a 0.2 % absolute accuracy for pulses with 500 ns peaking time, 2.7 V linear input range, 3.5 mW power dissipation, 250 mV/s droop rate, and negligible dead time. The use of such a high performance analog PDD can greatly relax the requirements on the digitization in multi-channel systems. 1 Work supported by the US Department of Energy, Contract No. DE-AC02-98CH10886. Patent pending.